1. Field of the Invention
The present invention relates to a Bi-MOS logic circuit incorporated in a Bi-MOS semiconductor IC which comprises bipolar transistors and MOS transistors--all formed on a single semiconductor chip--, and more particularly to a Bi-MOS logic circuit which is suitable as a D-type latch circuit or a D-type master-slave flip-flop circuit. 2. Description of the Related Art
The output buffer circuit used in most Bi-MOS logic circuits comprises NPN transistors. The NPN transistors are switched on or off by a drive circuit which has MOS transistors. The drive circuit, which comprises MOS transistors, consumes very little power, particularly when it has a CMOS structure. The output buffer circuit, which comprises NPN transistors, has a great current-driving ability. Hence, a Bi-MOS logic circuit is advantageous in two respects. First, it can operate at high speed. Second, it consumes but a little power.
FIG. 1 illustrates a conventional Bi-MOS logic circuit, which functions as a D-type latch circuit As is shown in FIG. 1, the logic circuit has an output buffer circuit which comprises an NPN transistor Q1 and a Schottky-barrier NPN transistor Q2. These transistors Q1 and Q2 are switched on or off by a drive circuit comprising four N-channel MOS transistors N1 to N4.
The Bi-MOS logic circuit can operate in two modes, a data-inputting mode and a data-latching mode. The logic circuit is set to the data-inputting mode when the clock signals CK and CKsupplied to it are at logic "1" level (hereinafter called `"1" level`) and logic "0" level (hereinafter called `"0" level`), respectively. It is set to the data-latching mode when the clock signals CK and CK are at "0" level and "1" level, respectively.
While the logic circuit is set to the data-inputting mode, the transistor N3 is turning on by the clock signal CK at "1" level, and the transistor N2 is turning off by the clock signal CK at "0" level. The current path between nodes A and B is either enabled or disabled, in accordance with whether the transistor N4 is turned on or off under the control of the data D input to the logic circuit.
More precisely, when the input data D is at "1" level, the transistor N4 is turned on, thus enabling the current path between the nodes A and B. In this case, a current flows from a power-supply terminal Vcc to the base of the transistor Q2 through a resistor R, the transistor N3, and the transistor N4. The transistor Q2 is thereby turned on. As a result of this, the output signal OUT of the logic circuit is at "0" level. At this time, the potentials of both nodes A and B are set at "0" level, i.e., approximately the base-emitter voltage (e.g., 1 V) of the transistor Q2 which is on. On the other hand, when the input data D is at "0" level, the transistor N4 is turned off, disabling the current path between the nodes A and B. In this case, a current flows from a power-supply terminal Vcc to the base of the transistor Q1 through the resistor R. The transistor Q1 is thereby turned on. As a result of this, the output signal OUT of the logic circuit is at "1" level. At this time, the potential of the node A is set at "1" level.
While the logic circuit is set to the data-latching mode, the clock signal CK at "0" level turns the transistor N3 off, and the clock signal CK at "1" level turns the transistor N2 on. The current path between nodes A and B is either enabled or disabled, in accordance with whether the transistor N1 is turned on or off under the control of the output of an inverter I1 which has inverted the potential of the node A.
As has been described, the potential at the node A is at the "1" level when the output signal OUT remains at the "1" level, that is, when the transistor Q1 is on, while the logic circuit is in the data-inputting mode. When the operating mode is changed in this condition, from the data-inputting mode to the data-latching mode, the transistor N1 remains off-state by virtue of the output of the inverter I1 which is at the "0" level. Hence, the current path between the nodes A and B is disable and the potential of node A is maintained at the "1" level. The output signal OUT of the logic circuit is thereby maintained at the "1" level, too. On the other hand, when the output signal OUT remains at the "0" level, that is, when the transistor Q2 is on, while the logic circuit is in the data-inputting mode, the potential at the node A is at the "0" level. When the operating mode is changed in this condition, from the data-inputting mode to the data-latching mode, the transistor N1 remains on-state by virtue of the output of the inverter I1 which is at the "1" level. Hence, the current path between the nodes A and B is enabled, and the potential of the node A is maintained at the "0" level. The output signal OUT of the logic circuit is thereby maintained at the "0" level, too.
As has been described, the Bi-MOS logic circuit shown in FIG. 1 outputs a signal OUT at the logic level opposite to that of the input data D while the circuit is in the data-inputting mode. Once it is set to the data-latching mode, its output signal OUT is maintained at the level same as that of the signal OUT when the circuit is in the data-inputting mode. When the logic circuit is set to the data-inputting mode again, it outputs a signal OUT which is at the level opposite to that of the input data D.
When its operation mode is changed from the data-latching mode, wherein the output signal OUT remains at the "0" level, to the data-latching mode wherein the output signal OUT remains at the "1" level (more precisely, when the circuit is set to the data-latching mode, thus maintaining its output signal OUT at the "0", it is set to the data-inputting mode and outputs a signal OUT at the "1" level, and further it it set to the data-latching mode again, thus maintaining the output signal OUT at the "1" level), the Bi-MOS logic circuit has the following problem.
In the data-latching mode, wherein the output signal OUT remains at the "0" level, the transistors N1 and N2 are on. When the operation mode of the logic circuit is changed to the data-inputting mode, the transistor N2 is turned off by the inverted clock signal CK at the "0" level. On the other hand, the transistor N1 remains on until the inverter I1 outputs a signal at the "0" level, that is, until the potential of the node A increases to the "1" level, thus turning the transistor Q1 on. While the transistor N1 is on, the parasitic capacitor C located at the node of the transistors N1 and N2 is continuously charged because of the current supplied from the power-supply terminal Vcc through the resistor R. When the operation mode of the logic circuit is switched from the data-inputting mode to the data-latching mode, the electrical charge accumulated in the parasitic capacitor C is released through the transistor N2, which has been turned on, and is supplied to the base of the transistor Q2. Obviously, not only the transistor Q1, but also the transistor Q2 remains on after the operation mode is changed to the data-latching mode and before the parasitic capacitor C is completely discharged. A current flows through these transistors Q1 and Q2, both being on, from the power-supply terminal Vcc to a ground terminal GND. Consequently, the logic circuit consumes much power, and the "1"-level potential of the output signal OUT decreases about 0.5 V.
As has been described, the conventional Bi-MOS logic circuit is disadvantageous in view of the large power consumption and the decrease in the "1"-level potential of the signal OUT, either resulting from the charge accumulated in the parasitic capacitor located at the node of the serial circuit constituted by the transistors N1 and N2.